Circuit for controlling an enabling time of an internal control signal according to an operating frequency of a memory device and the method thereof

ABSTRACT

Provided is a circuit for controlling a data bus connecting a bitline sense amplifier to a data sense amplifier in accordance with a variation of an operating frequency of a memory device, being comprised of a pulse width adjusting circuit for varying a pulse width of an input signal in accordance with the operating frequency of the memory device after receiving the input signal, a signal transmission circuit for buffing a signal outputted from the pulse width adjusting circuit, and an output circuit for outputting a first signal to control the data bus in response to a signal outputted from the signal transmission circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for controlling a senseamplifier of a memory device, and more particularly, to a method andcircuit for automatically controlling an operation of a sense amplifierin correspondence with variations of operating voltage and frequency ofa memory device.

2. Description of the Related Art

FIG. 1 is a diagram illustrating a read and write operations in ageneral memory device.

As shown in FIG. 1, during a write operation, data applied through aninput/output data pad is transferred to a bitline sense amplifierthrough a data input buffer and a data input register. While, during aread operation, cell data amplified by the bitline sense amplifier istransferred to the input/output data pad through a data sense amplifier,a pipe register, and a data output buffer.

In FIG. 1, signal Yi is a pulse signal to connect the bitline senseamplifier with the data sense amplifier so as to control an operation ofa data bus. While the signal Yi controlling the data bus is beingenabled, the write data is transferred to the bitline sense amplifierfrom a write driver and the read data is transferred to the data senseamplifier from the bitline sense amplifier. It is advantageous to make apulse width of the signal Yi wider in transferring valid data in anactive operation mode (the read or write operation). It is alsoefficient to improve the performance of tDPL (a time from when a CASpulse signal is generated internally by a write command to when aprecharge pulse signal is generated internally by a precharge command)because the time parameter tDPL contributes to making restoringfacilities of data better. Therefore, it is usual to establish the pulsewidth of the signal Yi as wider as possible within the permissible rangeand to use it with shrinking down in accordance with operationalconditions. In reference, as an operating frequency of a memory deviceincreases (i.e., a clock cycle period is shorter), a permissible pulsewidth of the signal Yi becomes narrower.

Meanwhile, as the signal Yi is made from responding to a read/writestrobe pulse signal rdwtatbzp13 output from a read/write strobe pulsegenerator, hereinafter will be explained about the read/write strobepulse generator.

FIG. 2A illustrates an example of a conventional read/write strobe pulsegenerator and FIG. 2B is a waveform diagram of signals used in thecircuit shown in FIG. 2A.

In FIG. 2A, signals extyp8 and icasp6 are signals to make a datatransmission line short or open, so as to read data to a peripheralcircuit from a cell array of the memory device or to write data in thecell array of the memory device from a peripheral circuit. Forinformation, it's named a core section for the range including a memorycell and a bitline sense amplifier and the rest a peripheral circuit.

In detail, the signal extyp8 is a pulse signal that is generated in syncwith a clock signal when a read or write command (burst command) isapplied to the memory device. And, the signal icasp6 is a signal to beused in operating the memory device by generating a self-burst operationcommand that is established with a burst length set by an MRS (moderegister set) mode from a clock time later by one clock cycle periodthan a clock time when a read or write command is applied from theexternal.

The signal rdwtstbzp13 is a signal to be active for the burst length setby the MRS mode, being activated in sync with the signals of the burstoperation command (external=exryp8 & internal=icasp61). In other words,the signal rdwtstbzp13 is to be used to inform an activation time of theinput/output sense amplifier in amplifying and transferring data, whichis to be sent to a peripheral circuit from a core circuit region, to thedata output buffer, resetting the data transmission line of theperipheral circuit after completing the data amplification andtransmission by the sense amplifier.

A signal pwrup is a signal to set an initial data value, retaining lowlevel after falling down to low level from high level. Signal term_z isa signal used in a test mode being held on low level during a normaloperation. A signal tm_clkpulsez is used in a test mode. Such signalswill be described in detail in conjunction with embodiments of thepresent invention hereinafter.

A circuit operation of FIG. 2A is illustrated, as follows, withreference to the waveform diagram of FIG. 2B.

As illustrated in FIG. 2B, when the read/write command is applied to thememory device in sync with the clock signal clock, the pulse signalextyp8 is generated. If the pulse signal extyp8 is enabled, a pluralityof pulse signals icasp6 is generated in sync with the next clocks insequence. As shown in FIG. 2B, the read/write strobe pulse signalrdwtstbzp13 is generated in sync with rising edges of the pulse signalsextyp8 and icasp6.

Here, in the conventional circuit shown in FIG. 2A, it can be seen thatthe pulse width of the read/write strobe pulse signal rdwtstbzp13generated from a pulse width adjusting circuit 200 is fixed neverthelessof the operating frequency of the memory device. Here, a delay time froma node A from a node D is determined by a delay circuit 20. As the delaytime of the delay circuit 20 in the pulse width adjusting circuit 200 isfixed, the pulse width of the signal outputted from the pulse widthadjusting circuit 200 is always constant without regarding to theoperating frequency of the memory device.

But, it needs to adjust a pulse width of the read/write strobe pulsesignal rdwtstbzp13 when an operating frequency of the memory devicevaries. In a conventional art, while the delay time of the delay circuit20 is variable by modifying a metal option during a FIB process when anoperating frequency of the memory device varies, it needs much costs andtimes.

In addition, with the conventional art, there is no way to correct avariation of the pulse width of the read/write strobe pulse signalrdwtstbzp13 when an operation voltage of the memory device varies.

SUMMARY OF THE INVENTION

Accordingly, the present invention has been made in an effort to solvethe problems occurring in the related art, and an object of the presentinvention is to provide a method of automatically controlling a pulsewidth of a signal output from a pulse width adjusting circuit inaccordance with variation of an operating frequency of a memory device.

Another object of the present invention is to provide a method ofcontrolling a pulse width of a read/write strobe pulse signalrdwtstbzp13 in correspondence with variation of an external clocksignal.

In order to achieve the above object, according to one aspect of thepresent invention, there is provided a read/write strobe pulse generatorgenerally usable even when an operating frequency of a memory devicevaries.

According to another aspect of the present invention, there is alsoprovided a method of delaying a signal outputted from a read/writestrobe pulse generator by applying an external address signal andcontrolling a width of the read/write pulse.

According to still another aspect of the present invention, what'sprovided is a method of controlling a pulse width of a read/write strobepulse signal rdwtstbzp13 in accordance with variation of an operationvoltage of a memory device.

By the features of the present invention, an embodiment of the presentinvention is a circuit for controlling an enabling period of an internalcontrol signal in accordance with variation of an operating frequency ina memory device, which comprises a pulse width adjusting circuit forchanging a pulse width of an input signal in accordance with theoperating frequency; a signal transmission circuit for buffing a signaloutputted from the pulse width adjusting circuit; and an output circuitfor outputting a first signal to control an operation of a data bus ofthe memory device in response to a signal output from the signaltransmission circuit.

In this embodiment, the pulse width adjusting circuit comprises a firstdelay circuit and a NAND gate, in which the NAND gate receives the inputsignal and an output signal of the first delay circuit, and the firstdelay circuit receives the input signal and a clock signal of the memorydevice and adjusts a delay time in accordance with a frequency of theclock signal until the input signal is applied to an input terminal ofthe NAND gate.

In this embodiment, as a cycle period of the clock signal is shorter, apulse width of the first signal is narrower.

Another embodiment of the present invention is a method for controllingan enabling period of an internal control signal in accordance withvariation of an operating frequency in a memory device, which comprisesthe steps of: (a) receiving an input signal; (b) delaying the inputsignal for a predetermined time; (c) operating the input signal and asignal delayed from the input signal in a NAND logic; and (d) outputtinga result of operating the NAND logic.

In this embodiment, it further comprises the step of: (b-1) determiningthe predetermined time of the step (b) in accordance with a frequency ofa clock signal of the memory device.

In this embodiment, as the frequency of the clock signal increases, apulse width of a signal outputted from the step (d) is narrower.

In this embodiment, it further comprises the step of (b-2) more reducinga pulse width of a signal outputted from the step (d) by using anaddress signal of the memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects, and other features and advantages of the presentinvention will become more apparent after a reading of the followingdetailed description when taken in conjunction with the drawings, inwhich:

FIG. 1 is a diagram illustrating a read and write operation in a generalmemory device;

FIG. 2A illustrates an example of a conventional read/write strobe pulsegenerator;

FIG. 2B is a waveform diagram of signals used in the circuit shown inFIG. 2A;

FIG. 3 illustrates an exemplary embodiment of a read/write strobe pulsegenerator in accordance with the present invention;

FIGS. 4 through 10 illustrate embodiments of a delay circuit 30 in apulse width adjusting circuit 300 shown in FIG. 3;

FIG. 11 is an operational timing diagram of the conventional circuitshown in FIG. 2A;

FIG. 12 is a waveform diagram illustrating a pulse width variation ofthe read/write strobe pulse signal rdwtstbzp13 output from theconventional circuit of FIG. 2A when an operation voltage vdd of amemory device varies;

FIG. 13 is a waveform diagram of signals used in the circuit of thepresent invention, specifically an exemplary waveform diagram of signalsused in the circuit of FIG. 5;

FIG. 14 is a diagram illustrating a procedure of changing logical levelsof flag signals Flag1 and Flag 2 in accordance with a frequency of aclock signal clk_in;

FIG. 15 is a diagram illustrating a waveform of an output signalrdwtstbzp13 when paths C1 and C2 shown in FIG. 10 are used therein; and

FIG. 16 is a waveform diagram illustrating a variation of the outputsignal rdwtstbzp13 in accordance with a variation of the operationvoltage.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Reference will now be made in greater detail to a preferred embodimentof the invention, an example of which is illustrated in the accompanyingdrawings. Wherever possible, the same reference numerals will be usedthroughout the drawings and the description to refer to the same or likeparts.

FIG. 3 illustrates an exemplary embodiment of a read/write strobe pulsegenerator in accordance with the present invention.

The circuit of FIG. 3 is different from the circuit of FIG. 2A in that adelay circuit 30 in a pulse width adjusting circuit 300 is controlled bya clock signal clk_in and address signals add_0 and add_1.

The circuit of FIG. 3 is comprised of an input signal receiver 310, apulse width adjusting circuit 300, a signal transmission circuit 320, atest mode circuit 330, and an output circuit 340.

The input signal receiver 310 includes inverters INV30 and INV31, and aNAND gate NAND30. An input signal extyp8 is applied to the inverterINV30 and an input signal icasp6 is applied to the inverter INV31.Output signals of the inverters INV30 and INV31 are applied to the NANDgate NAND30.

The pulse width adjusting circuit 300 includes the delay circuit 30 andthe NAND gate NAND31.

The delay circuit 30 receives an output signal of the NAND gate NAND30,a test mode signal tmz_1, the clock signal clk_in, and the addresssignals add_0 and add_1.

The NAND gate NAND31 receives the output signal of the NAND gate NAND30and an output signal of the delay circuit 30. An output signal of thepulse width adjusting circuit 300 is an output signal of the NAND gateNAND31. A delay time from a node A to a node D is determined by thedelay circuit 30. The delay time by the delay circuit 30 is adjustableby means of a frequency of the clock signal clk_in and the addresssignals add_0 and add_1. In reference, the test mode signal tmz_1 is acontrol signal to determine whether or not a current operation is a testmode, retaining low level during the test mode while retaining highlevel during a normal operation mode. The add_0 and add_1 are externaladdress signals to be used in the test operation mode. Functions of thesignals will be explained relative to the detail circuit hereinafter.

The signal transmission circuit 320 includes inverters INV32, INV33, andINV34 that receive and buff the signal outputted from the pulse widthadjusting circuit 300.

The test mode circuit 330 includes transistors P31, P32, and N31 and alatch circuit 301. As illustrated in FIG. 3, the PMOS transistor P31 andthe NMOS transistor N31 are connected between a power source voltage anda ground in series. The PMOS transistor P32 is connected between thepower source voltage and a node NODE31. The latch 301 temporarily storesa signal of the node NODE31. Here, termz is a signal used in the testmode and the signal pwrup is that as stated in FIG. 2A.

The output circuit 340 includes a NAND gate 302 and inverters INV35 andINV36. The NAND gate 302 receives an output signal of the inverterINV34, the signal termz, and an output signal of the latch circuit 301.The signal termz functions to inhibit the read/write strobe pulse signalrdwtstbzp13. An output signal of the NAND gate 302 is applied to theinverters INV35 and INV36 serially connected from each other. An outputsignal of the inverter INV36 as an output signal of the output circuit340 becomes the read/write strobe pulse signal rdwtstbzp13.

In a normal operation, the input signals extyp8 and icasp6 are generatedinto the read/write strobe pulse signal rdwtstbzp13 after apredetermined time. During this, it is possible for the pulse widthadjusting circuit 300 to control a pulse width of the read/write strobepulse signal rdwtstbzp13 by modifying a pulse width of the input signalsextyp8 and icasp6 with using the clock signal clk_in that variesdependent on variation of an operating frequency.

FIGS. 4 through 10 illustrate embodiments of the delay circuit 30 in thepulse width adjusting circuit 300 shown in FIG. 3. As described later,the clock signal clk_in is applied to the delay circuit 30 so as todetect an operating frequency of the memory device. And, at thebeginning of the test mode, the test mode signal tmz_1 of low level isapplied thereto. Also, at the beginning of the test mode, the addresssignals add_0 and add_1 are applied to further tune a delay time. Inreference, the node A and D shown in FIG. 3 correspond to those node Aand D shown in FIG. 4.

Hereinafter, it will be described in more detail about the circuitsshown in FIGS. 4 through 10.

FIG. 4 is a block diagram illustrating an internal structure of thedelay circuit shown in FIG. 3 in detail.

As illustrated in FIG. 4, the delay circuit 30 in FIG. 3 is comprised ofdelay units 401, 402, and 403, a frequency detector 404, a voltagedetector 405, a test mode address signal receiver 406, and a referencevoltage generator 407. Exemplary circuits of the frequency detector 404,the voltage detector 405, and the test mode address signal receiver 406are shown in FIGS. 4, 5, and 6, respectively.

In FIG. 4, the frequency detector 404 receives the clock signal clk_inand then outputs operating frequency detection signals dec_0z, dec_1z,and dec_2z which control a delay path of the delay unit 401. Logicallevels of the operating frequency detection signals dec_0z, dec_1z, anddec_2z vary in accordance with a frequency of the clock signal clk_in.The delay path from the node A to the node D is alterable in accordancewith a frequency of the clock signal clk_in.

The reference voltage generator 407 is enabled by the power-up signalpwrup, outputting a plurality of reference voltages vref_0 and vref_1.The reference voltage generator 407 is a circuit capable of outputtingstable reference voltages without affecting from an operation voltage,which is constructed with circuit structures well known by those skilledin this art.

The voltage detector 405 detects a variation of the operation voltagevdd by comparing the operation voltage vdd to the reference voltagesvref_0 and vref_1. The voltage detector 405 outputs a plurality ofvoltage selection signals vsel_0z, vsel_1z, and vsel_2z to control thedelay path of the delay unit 402. Thus, delay times of delay paths B˜C1are determined by logical level of the voltage selection signalsvsel_0z, vsel_1z, and vsel_2z.

In accordance with a logical level of the test mode signal tmz_1, asignal of the node C1 can be transferred to the node D directly orthrough the delay unit 403. When the test mode signal tmz_1 is highlevel, the signal of the node C1 is transferred directly to the node D.

The test mode address signal receiver 406 receives an address signal andoutputs a plurality of selection signals sel_0z, sel_1z, sel_2z, andsel_3z. Responding to the selection signals sel_0z, sel_1z, sel_2z, andsel_3z, a delay time of the delay unit 403 is adjusted. Asaforementioned, the delay unit 403 is used as a delay path in the testmode, which means that it is possible to conduct an additional delaytuning operation by using the address signal when the test mode signaltmz_1 is being low level.

Exemplary features of the components shown in FIG. 4 are illustrated inFIGS. 5 through 10.

FIG. 5 illustrates, as an example of the frequency detector 404 shown inFIG. 4, a circuit for outputting the operating frequency detectionsignals dec_0z, dec_1z, and dec_2z that determine a range of theoperating frequency of the memory device in response to the clock signalclk_in.

In FIG. 5, after detecting an operating frequency of the memory deviceby generating a plurality of internal signals dlic4_ref, dlic4, dlic4d1,dlic4d2, cmp, flag_1, and flag_2 in response to the clock signal clk_in,the operating frequency detection signals dec_0z, dec_1z, and dec_2z arefinally outputted therefrom to be determined the range of the operatingfrequency of the memory device.

As illustrated in FIG. 5, the clock signal clk_in is applied to afrequency divider 500. The divider 500_outputs the frequency dividingsignal dlic4_ref having a period longer than that of the clock signalclk_in. As shown in the waveform diagram of FIG. 13, a cycle period ofthe frequency dividing signal dlic4_ref is four times of that of theclock signal clk_in. At this case, a low level term of the frequencydividing signal dlic4_ref is identical to the cycle period tCLK of theclock signal clk_in. However, the cycle period of the frequency dividingsignal dlic4_ref may be alterable by those skilled in this art.

The frequency dividing signal dlic4_ref is outputted with phaseinversion after being delayed by a buffer circuit 501 composed ofodd-numbered inverters. The phase-inversed frequency dividing signal isdenoted as dlic4. Waveforms of those signals dlic4_ref and dlic4 areshown in FIG. 13.

In FIG. 5, the frequency dividing signal dlic4_ref and thephase-inversed frequency dividing signal dlic4 are applied to a NANDgate NAND51. An output signal from the NAND gate NAND51 is applied to adelay unit 506 and a NOR gate NOR51. The NOR gate NOR51 receives theoutput signal of the NAND gate NAND51 and an output signal of the delayunit 506, and outputs the pulse signal cmp. The output signal cmp of theNOR gate NOR51 is illustrated in FIG. 13. The phase-inversed frequencydividing signal dlic4 is applied to delay units delay_A and delay_B.Here, there is a difference between delay times of the delay unitsdelay_A and delay_B. Output signals of the delay units delay_A anddelay_B are represented to as dlic4d1 and dlic4d2, respectively.

The output signal dlic4d1 of the delay unit delay_A and the frequencydividing signal dlic4_ref are applied to a flipflop circuit 502. Theflipflop circuit 502 is constructed of two NAND gates input/outputterminals of which are cross-coupled each other. Output signals from twooutput terminals of the flipflop circuit 502 are e and f, respectively.

The output signal dlic4d2 of the delay unit delay_B and the frequencydividing signal dlic4_ref are applied to a flipflop circuit 503. Theflipflop circuit 503 is constructed of two NAND gates input/outputterminals of which are cross-coupled each other. Output signals from twooutput terminals of the flipflop circuit 503 are g and h, respectively.

A NAND gate NAND52 receives the output signal cmp of the NOR gate NOR51and the output signal e of the flipflop circuit 502. A NAND gate NAND53receives the output signal cmp of the NOR gate NOR51 and the outputsignal f of the flipflop circuit 502. A NAND gate NAND54 receives theoutput signal cmp and the output signal g of the flipflop circuit 503. ANAND gate NAND55 receives the output signal cmp of the NOR gate NOR51and the output signal h of the flipflop circuit 503.

Output signals of the NAND gates NAND52 and NAND53 are applied to theflipflop circuit 504. The flipflop circuit 504 is constructed of twoNAND gates input/output terminals of which are cross-coupled each other.An output signal of the flipflop circuit 504 is represented to as a flagsignal flag_1.

Output signals of the NAND gates NAND54 and NAND55 are applied to theflipflop circuit 505. The flipflop circuit 505 is constructed of twoNAND gates input/output terminals of which are cross-coupled each other.An output signal of the flipflop circuit 505 is represented to as a flagsignal flag_2.

In reference, when a delay time by delay unit 508 is longer than that bydelay unit 507 (i.e.. delay_A<delay_B), logical levels of the flagsignals are as follows.

If tCLK<delay_A, the flag signals flag_1 and flag_2 are all low levels.Here, tCLK is a cycle period of the clock signal clk_in.

If delay_A<tCLK<delay_B, the flag signal flag_1 is high level while theflag signal flag_2 is low level.

If tCLK>delay_B, the flag signal flag_1 and flag_2 are all high levels.

In FIG. 5, the flag signals flag_1 and flag_2 are applied each toinverters INV51 and INV52. Output signals of the inverters INV51 andINV52 are applied to NAND gate NAND56. The NAND gate NAND56 outputs theoperating frequency detection signal dec_0z.

Next, the flag signal flag_2 is applied to an inverter INV53. An outputsignal of the inverter INV53 and the flag signal flag_1 are applied to aNAND gate NAND57. The NAND gate NAND57 outputs the operating frequencydetection signal dec_1z.

Finally, the flag signals flag_1 and flag_2 are applied to a NAND gateNAND58. The NAND gate NAND58 outputs the operating frequency detectionsignal dec_1z.

FIG. 6 is a circuit for outputting voltage selection signals vsel_2z,vsel_1z, and vsel_0z so as to control a delay time of an input signal inaccordance with variation of an operation voltage. The voltage selectionsignals generated in FIG. 6 are used for selecting a delay path of acircuit shown in FIG. 9.

FIG. 6 illustrates two differential amplifying comparators. As shown inFIG. 6, there are a differential amplifying comparator for comparing theoperation voltage vdd to the reference voltage vref_0 and anotherdifferential amplifying comparator for comparing the operation voltagevdd to the reference voltage vref_1. The reference voltage vref_0 islower than the reference voltage vref_1 (vref_0<vref_1).

As noticed from FIG. 6, if vdd<vref_0, output signals DET_0 and DET_1 ofthe differential amplifying comparator are all high levels.

If vref_0<vdd<vref_1, the output signal DET_0 is high level while theoutput signal DET_1 is low level.

If vdd>vref_1, the output signals DET_0 and DET_1 of the differentialamplifying comparator are all low levels.

The output signal DET_0 of the differential amplifying comparator isapplied to an inverter INV61 and an output signal of the inverter INV61is DET_0b. The output signal DET_1 of the differential amplifyingcomparator is applied to an inverter INV62 and an output signal of theinverter INV62 is DET_1b.

In FIG. 6, NAND gate NAND61 receives the signals DET_0b and DKT_1b andan output signal of the NAND gate NAND61 is the voltage selection signalvsel_2z.

A NAND gate NAND62 receives the signals DET_0b and DET_1b and an outputsignal of the NAND gate NAND62 is the voltage selection signal vsel_1z.

A NAND gate NAND63 receives the signals DET_0 and DET_1 and an outputsignal of the NAND gate NAND63 is the voltage selection signal vsel_0z.

As can be seen by FIG. 6, the circuits of FIG. 6 are provided to detecta fluctuation of the operation voltage vdd relative to the referencevoltages vref_0 and vref_1.

FIG. 7 illustrates circuit elements for generating the selection signalssel_3z, sel_2z, sel_1z, and sel_0z to designate delay paths in responseto the address signals add_0 and add_1.

As illustrated in FIG. 7, an inverter INV71 receiving the address signaladd_0 outputs a phase-inversed address signal add_0b. An inverter INV72receiving the address signal add_1 outputs phase-inversed address signaladd_1b. Next, the delay path selection signals sel_3z, sel_2z, sel_1z,and sel_0z are generated resulting from logical combinations with theaddress signals. That is, the NAND gate NAND71 receives the addresssignals add_0b and add_1b and then outputs the selection signal sel_3z.The NAND gate NAND72 receives the address signals add_0b and add_1 andthen outputs the selection signal sel_2z. The NAND gate NAND73 receivesthe address signals add_0 and add_1b and then outputs the selectionsignal sel_1z. The NAND gate NAND74 receives the address signals add_0and add_1 and then outputs the selection signal sel_0z.

FIG. 8, as an exemplary feature of the delay circuit 30, shows anexample of a circuit for selecting a delay path of an input signal withusing the operating frequency detection signals dec_0z, dec_1z, anddec_2z that are generated in FIG. 5.

The circuit of FIG. 8 comprises a plurality of delay units 801, 802,803, and 804, and switching units 811, 812, 814, 815, and 816 which arecontrolled by the operating frequency detection signals dec_0z, dec_1z,and dec_2z. Each of modulation circuits 817 and 818 is composed of aNAND gate and an inverter which are connected in series. Input terminalsof the modulation circuits 817 and 818 receive a signal of the node A.

In FIG. 8, the whole delay time is taken from the node A to the node D.Here, the nodes A and D of FIG. 8 are the same with the nodes A and D ofFIG. 3.

A signal input through the node A of FIG. 8 is an output signal from theinput signal receiver 310 of FIG. 3, which is the signal extyp8 oricasp6.

In FIG. 8, the operating frequency detection signals dec_1z and dec_2zcontrol turn-on/off operations of the switching units 811 and 814. Theoperating frequency detection signal dec_0z controls a turn-on/offoperation of the switching unit 812. The operating frequency detectionsignal dec_2z controls a turn-on/off operation of the switching unit815. The test mode signal tmz_1 controls a turn-on/off operation of theswitching unit 816.

In operation, when a NAND gate NAND81 receiving the operating frequencydetection signals dec_1z and dec-2z outputs a high-level output signal,the switching units 811 and 814 are turned on. Thus, the input signalreceived through the node A passes by way of the delay unit 801, themodulation circuit 817, the delay unit 802, the modulation circuit 818,and the switching unit 814, in sequence. Here, the switching unit 815 iscontrolled by the operating frequency detection signal dec_2z.Therefore, while a signal passing through the switching unit 814 istransferred to the node B through the delay unit 804 when the operatingfrequency detection signal dec_2z is low level, it is transferreddirectly to the node C when the operating frequency detection signaldec_2z is high level.

In operation, when the switching unit 812 is turned on in response tothe operating frequency detection signal dec_0z, the input signalreceived through the node A passes by way of the delay unit 801, themodulation circuit 817, and the switching unit 812, in sequence. Here,the switching unit 815 is controlled by the operating frequencydetection signal dec_2z. While a signal passing through the switchingunit 812 is transferred to the node B through the delay unit 804 whenthe operating frequency detection signal dec_2z is low level, it istransferred directly to the node B when the operating frequencydetection signal dec_2z is high level.

Next, a signal on the node B is transferred to the node C1 through theswitching unit 816. A signal at the node C may be transferred to thenode D through the switching unit 816 directly or transferred to thenode D through the delay path of C1-C2-D.

Hereinafter, it will be described in detail about the alternativedelaying operations.

Referring to FIG. 8, the switching unit 816 is turned on/off by the testmode signal tmz_1. In a test mode, the test mode signal tmz_1 retainslow level. In a normal operation mode, the test mode signal tmz_1retains high level.

In the normal operation mode, a signal on the node C1 is forwarded to adelay path of C1-D. In other words, the signal on the node C1 istransferred to the node D by way of the switching unit 816, an inverterINV81, and a NAND gate NAND83. Here, the NAND gate NAND83 receivessignals output from the inverter INV81 and the node A.

In the test mode, the signal on the node C1 is transferred to the nodeC2 through the circuit shown in FIG. 10. The signal transferred to thenode C2 is transferred to the node D by way of the switching unit 816,the inverter INV81, and the NAND gate NAND83.

FIG. 9 illustrates a circuit disposed on a delay path of B-C1. The delaypath circuit of FIG. 9 is selected by the voltage selection signalsvsel_2z, vsel_1z, and vsel_0z which are generated in FIG. 6.

As illustrated, the circuit of FIG. 9 is comprised of delay units 901,902, and 903, switching units 911, 912, 913, and 914, and NAND gatesNAND91 and NAND92.

The NAND gates NAND91 and NAND92 receive the voltage selection signalsvsel_1z and vsel_0z. The switching unit 911 is turned on/off by anoutput signal of the NAND gate NAND91. The switching unit 913 is turnedon/off by an output signal of the NAND gate NAND92. The switching unit912 is turned on/off by the voltage selection signal vsel_2z. Theswitching unit 914 is turned on/off by the voltage selection signalvsel_0z.

In operation, if the switching units 911 and 913 are turned on, a signalon the node B passes through the delay unit 901, the switching unit 911,the delay unit 911, and the switching unit 913, in sequence. A delaypath of the signal passing through the switching unit 913 is alterablein accordance with the voltage selection signal vsel_0z. That is, whenthe voltage selection signal vsel_0z is high level, the signal passingthrough the switching unit 913 is transferred to the node C1 by way ofthe switching unit 914. Otherwise, when the voltage selection signalvsel_0z is low level, the signal passing through the switching unit 913is transferred to the node C1 by way of the delay unit 903 and theswitching unit 914.

In operation, if the switching unit 912 is turned on, a signal on thenode B passes through the delay unit 901 and the switching unit 912. Adelay path of the signal passing through the switching unit 912 isalterable in accordance with the voltage selection signal vsel_0z. Thatis, when the voltage selection signal vsel_0z is high level, the signalpassing through the switching unit 912 is transferred to the node C1 byway of the switching unit 914. Otherwise, when the voltage selectionsignal vsel_0z is low level, the signal passing through the switchingunit 912 is transferred to the node C1 by way of the delay unit 903 andthe switching unit 914.

FIG. 10 , as an exemplary feature of a circuit interposed between thenodes C1 and C2, illustrates a circuit for controlling a delay rate withusing address signals in a test mode (when tmz_1 of FIG. 8 is lowlevel).

The circuit of FIG. 10 is comprised of delay units 1000, 1001, 1002,1003, and 1004, switching units 1011, 1012, 1013, 1014, and 1015 whichare controlled by the selection signals sel_3z, sel_2z, sel_1z, andsel_0z, and conversion circuits 1017 and 1018. Each of the conversioncircuits 1017 and 1018 is a NAND gate and an inverter which areconnected in series. A signal of the node C1 is inputted through inputterminals of the conversion circuits 1017 and 1018. In FIG. 10, thewhole delay time is taken from the node C1 to the node C2. Here, thenodes C1 and C2 are identical to the nodes C1 and C2 shown in FIG. 8.And, a signal of the node C1 is inputted through an input terminal ofNAND gate NAND103.

As stated above in connection with FIG. 7, the selection signals sel_3z,sel_2z, sel_1z, and sel_0z, which control turn-on/off operations of theswitching units, are made from logical combinations with addresssignals.

As can be seen from FIGS. 7 and 10, when the address signals add_0 andadd_1 are all low levels, the selection signal sel_3z is enabled in lowlevel. When the address signals add_0 and add_1 are respectively low andhigh levels, the selection signal sel_2z is enabled in low level. Whenthe address signals add_0 and add_1 are respectively high and lowlevels, the selection signal sel_1z is enabled in low level. When theaddress signals add_0 and add_1 are all high levels, the selectionsignal sel_0z is enabled in low level.

In FIG. 10, NAND gates NAND101 and NAND102 receive the selection signalssel_2z and sel_3z. The switching unit 1011 is turned on/off by an outputsignal of the NAND gate NAND101. The switching unit 1014 is turnedon/off by an output signal of the NAND gate NAND102. The switching unit1012 is turned on/off by the selection signal sel_1z. The switching unit1013 is turned on/off by the selection signal sel_0z. The switching unit1015 is turned on/off by the selection signal sel_3z.

In operation, when the selection signals sel_2z and sel_3z are all lowlevels, an output signal of the NAND gate NAND101 receiving theselection signals sel_2z and sel_3z is high level. Thus, the switchingunits 1011 and 1014 are turned on. As a result, a signal receiverthrough the node C1 passes through the delay units 1000 and 1001, theconversion circuit 1017, the delay unit 1001, the switching unit 1011,the delay unit 1001, the conversion circuit 1018, and the switching unit1014, in sequence. Here, if the selection signal sel_3z is low level,the signal passing through the switching unit 1014 is transferred to thenode C2 by way of the NAND gate NAND103 and inverter INV101 afterpassing through the delay unit 1004 and the switching unit 1015.Otherwise, if the selection signal sel_3z is high level, the signalpassing through the switching unit 1014 is transferred to the node C2 byway of the switching unit 1015, the NAND gate NAND103, and inverterINV101. Therefore, when the selection signals sel_2z and sel_3z are alllow levels, the signal passing through the switching unit 1014 istransferred to the node C2 by way of the NAND gate NAND103 and theinverter INV101 after passing through the delay unit 1004.

In operation, when the selection signal sel_1z is low level, theswitching unit 1012 is turned on. Thus, a signal input through the nodeC1 passes through the delay units 1000 and 1001, the conversion circuit1017, the delay unit 1002, and the switching unit 1012, in sequence. Ifthe selection signal sel_3z is low level, the signal passing through theswitching unit 1012 is transferred to the node C2 by way of the NANDgate NAND103 and the inverter INV101 after passing through the delayunit 1004 and the switching unit 1015. Otherwise, if the selectionsignal sel_3z is high level, the signal passing through the switchingunit 1012 is transferred to the node C2 by way of the switching unit1015, the NAND gate NAND103, and the inverter INV101.

In operation, when the selection signal sel_0z is low level, theswitching unit 1013 is turned on. Thus, a signal input through the nodeC1 passes through the delay unit 1000 and the switching unit 1013, insequence. If the selection signal sel_3z is low level, the signalpassing through the switching unit 1013 is transferred to the node C2 byway of the NAND gate NAND103 and inverter INV101 after passing throughthe delay unit 1004 and the switching unit 1015. Otherwise, if theselection signal sel_3z is high level, the signal passing through theswitching unit 1013 is transferred to the node C2 by way of theswitching unit 1015, the NAND gate NAND103, and inverter INV101.

As illustrated in FIG. 10, in the test mode, it is possible to adjust adelay time taken from the node C1 to the node C2 by using the selectionsignals generated from logical combinations with the external addresssignals add_0 and add_1. For example, when the test mode signal tmz_1 ishigh level, the delay path between the nodes C1 and C2 is inhibited.

But, if the test mode signal tmz_1 is low level, the delay path betweenthe nodes C1 and C2 is open and adjustable by means of the selectionsignals.

FIG. 11 is an operational timing diagram of the conventional circuitshown in FIG. 2A.

As can be seen from FIG. 11, the conventional circuit is just capable ofadjusting only a pulse width of the output signal rdwtstbzp13 inaccordance with a logical level of a signal tmz_clkpulsez.

FIG. 12 is a waveform diagram illustrating a pulse width variation ofthe read/write strobe pulse signal rdwtstbzp13 output from theconventional circuit of FIG. 2A when an operation voltage vdd of amemory device varies.

As illustrated in FIG. 12, the conventional circuit has a problem that apulse width of the read/write strobe pulse signal rdwtstbzp13 decreaseswhen the operation voltage rises.

FIG. 13 is a waveform diagram of signals used in the circuit of thepresent invention, specifically an exemplary waveform diagram of signalsused in the circuit of FIG. 5. FIG. 13 illustrates waveforms of theclock signal clk_in, the frequency dividing signal dlic4_ref, thephase-inversed frequency dividing signal dlic4, the delay signalsdlic4d1 and dlic4d2, the pulse signal cmp, the flag signals flag_1 andflag_2, and the operating frequency detection signals dec_0z, dec_1z,and dec_2z.

In FIG. 13, the cycle period of the frequency dividing signal dlic4_refis four times of tCLK. And, the low level term of the frequency dividingsignal dlic4_ref is identical to that of tCLK. The phase-inversedfrequency dividing signal dlic4 is opposite to the frequency dividingsignal dlic4_ref in phase and generated with a predetermined delay time.

The phase-inversed frequency signal dlic4 is outputted as the delaysignal dlic4d1 after passing through the delay unit having the delaytime of delay_A. The phase-inversed frequency dividing signal dlic4 isalso outputted as the delay signal dlic4d2 after passing through thedelay unit having the delay time delay_B. At this case, thephase-inversed frequency dividing signal dlic4 and the delay signalsdlic4d1 and dlic4d2 have high level terms as same as that of tCLK. InFIG. 13, it is established of delay_A<delay_B.

Hereinafter, it will be described in detail about the signal waveformdiagram of FIG. 8 with reference to the circuit of FIG. 4.

In the condition of that the frequency dividing signal dlic4-ref, thedelay signal dlic4d1 and the pulse signal cmp are all high levels,initial values of the nodes e, f, g, and h in FIG. 4 are all highlevels. In this condition, if the delay signal dlic4d1 changes to highlevel earlier than the frequency dividing signal dlic4_ref, the node etransits to low level. Next, when the pulse signal amp transits to highlevel, the node h transits to low level. Thus, the flag signal flag_1becomes high level.

On the other hand, if the frequency dividing signal dlic4_ref changes tohigh level earlier than the delay signal dlic4d1, the node f transits tolow level. Next, when the pulse signal amp transits to high level, thenode g transits to low level. Thus, the flag signal flag_1 becomes lowlevel.

As described above, it is important in FIG. 5 that it determines alogical level of the flag signal flag_1 in accordance with which one ofthe two signals dlic4_ref and dlic4d1 to be compared transits to highlevel earlier before the pulse signal amp goes to high level.

A procedure of generating the flag signal flag_2 is substantiallyidentical to that of the flag signal flag_1, so will be omitted aboutit.

On the other side, the delay rates represented by delay_A and delay_Bare provided to detect a frequency range of the clock signal clk_in. Forinstance, in FIG. 13, the fact that a rising edge of the delay signaldlic4d1 is earlier than that of the frequency dividing signal dlic4_refmeans that the delay rate of delay_A is smaller than the cycle period ofthe clock signal clk_in. As such, the fact that a rising edge of thedelay signal dlic4d2 is later than that of the frequency dividing signaldlic4_ref means that the delay rate of delay_B is larger than the cycleperiod of the clock signal clk_in. Therefore, such cases form therelation of delay_A<tCK<delay_B. FIG. 13 illustrates waveform featuressatisfying the conditional relation.

FIG. 14 is a diagram illustrating a procedure of changing logical levelsof the flag signals flag_1 and flag_2 in accordance with a frequency ofthe clock signal clk_in. For sections A, B, and C of FIG. 14, it can beseen of delay_A<delay_B.

When tCK<delay_A as like the section A of FIG. 14, the flag signalsflag_1 and flag_2 are all low levels.

When delay_A<tCK<delay_B as like the section B of FIG. 14, the flagsignal flag_1 is high level while flag_2 is low level.

When tCK>delay_B as like the section C of FIG. 14, the flag signalsflag_1 and flag_2 are all high levels.

As such, it can be understood that the flag signals include theinformation for the operating frequency of the memory device. With thoseflag signals, logical levels of the operating frequency detectionsignals dec_0z, dec_1z, and dec_2z are determined to select the delaypath in the circuit shown in FIG. 8.

FIG. 15 is a diagram illustrating a waveform of the output signalrdwtstbzp13 when paths C1 and C2 shown in FIG. 10 are used therein. Asaforementioned, the circuit of FIG. 10 is to be used in the test modethat begins in response to the test mode signal tmz_1 shown in FIG. 8.In other words, the delay time is further adjustable by applying theaddress signals during the test mode.

The selection signals sel_3z, sel_2z, sel_1z, and sel_0z are generatedfrom logical combinations with the address signals as aforementionedwith reference to FIG. 7.

Section A of FIG. 15 illustrates waveforms of the input signal extyp8and the output signal rdwtstbzp13 when the operating frequency detectionsignals dec_2z and dec_1z are all high levels while the operatingfrequency detection signal dec_0z is low level.

Section B of FIG. 15 illustrates waveforms of the input signal extyp8and the output signal rdwtstbzp13 when the operating frequency detectionsignals dec_0z and dec_2z are all high levels while the operatingfrequency detection signal dec_1z is low level.

Section C of FIG. 15 illustrates waveforms of the input signal extyp8and the output signal rdwtstbzp13 when the operating frequency detectionsignals dec_0z and dec_1z are all high levels while the operatingfrequency detection signal dec_2z is low level.

As can be seen from the sections A, B, and C in FIG. 15, a pulse widthof the output signal rdwtstbzp13 is variable in accordance with logicallevels of the operating frequency detection signals dec_0z, dec_1z, anddec_2z which contain the information for the operating frequency of thememory device. Further, the pulse width of the output signal rdwtstbzp13is also variable in accordance with logical levels of the selectionsignals sel_0z, sel_1z, sel_2z, and sel_3z when the logical levels ofthe operating frequency detection signals dec_0z, dec_1z, and dec_2z areequal from each other (e.g, in the section A).

FIG. 16 is a waveform diagram illustrating a variation of the outputsignal rdwtstbzp13 in accordance with a variation of the operationvoltage.

As illustrated in FIG. 16, it can be seen that the pulse width of theoutput signal rdwtstbzp13 is variable in accordance with logical levelsof the voltage selection signals vsel_2z, vsel_1z, and vsel_0z. In theconventional circuit as shown in FIG. 12, a pulse width of the outputsignal rdwtstbzp13 decreases along an increase of the operation voltagevdd. However, the present invention is configured, as shown in FIG. 16,with that the pulse width of the output signal rdwtstbzp13 does notdecrease even along an increase of the operation voltage vdd. Such aresult of simulation, as illustrated in FIG. 16, is just provided fornotifying an improvement by the present invention over the conventionalart. It is also possible to enable the pulse width of the output signalrdwtstbzp13 to be stable by properly selecting the delay path by meansof the voltage selection signals even when the operation voltage varies.

As apparent from the above description, the present invention provides amethod and circuit for controlling a pulse width of the read/writestrobe pulse signal rdwtstbzp13 to control an operation of an Yi pulsesignal by detecting an operating frequency of the memory device.

By utilizing the method and circuit according to the present invention,the pulse width of the read/write strobe pulse signal rdwtstbzp13 isoptimally adjusted to control an enabling period of the Yi pulse signal.

With the method and circuit of the present invention, as it is possibleto automatically adjust a pulse width of the Yi signal, there is no needof an FIB process for tuning delay times whenever an operating frequencyvaries. Therefore, it downs costs and times relative to the conventionalcase.

Moreover, the present invention offers a reliable operation by reducinga pulse width variation of the read/write strobe pulse signal when anoperation voltage varies.

In the drawings and specification, there have been disclosed typicalpreferred embodiments of the invention and, although specific terms areemployed, they are used in a generic and descriptive sense only and notfor purposes of limitation, the scope of the invention being set forthin the following claims.

1. A circuit for controlling an enabling period of an internal controlsignal in accordance with variation of an operating frequency in amemory device, the circuit comprising: a pulse width adjusting circuitcomprised of a first delay circuit and a NAND gate at least one of aNAND gate and a NOR gate, which changes a pulse width of an input signalin accordance with the operating frequency, said NAND gate at least oneof a NAND gate and a NOR gate receiving the input signal and an outputsignal of the first delay circuit, the first delay circuit receiving theinput signal and a clock signal of the memory device and adjusting adelay time in accordance with a frequency of the clock signal until theinput signal is applied to an input terminal of the NAND gate at leastone of a NAND gate and a NOR gate; a signal transmission circuit forbuffering a signal outputted from the pulse width adjusting circuit; andan output circuit for outputting a first signal to control an operationof a data bus of the memory device in response to a signal outputtedfrom the signal transmission circuit, wherein as the clock signalduration shortens, the pulse width of the first signal is narrower. 2.The circuit of claim 1 wherein the first delay circuit comprises asecond delay circuit for receiving the input signal and a third delaycircuit for receiving a signal transferred from the second delaycircuit: wherein a delay time of the second delay circuit varies inaccordance with variation of the frequency of the clock signal; whereina delay time of the third delay circuit varies in accordance withvariation of an operation voltage of the memory device; and wherein anoutput signal of the third delay circuit is applied to the NAND gate atleast one of a NAND gate and a NOR gate.
 3. The circuit of claim 2,wherein the first delay circuit further comprises: a frequency detectorfor detecting variation of the frequency of the clock signal; and avoltage detector for detecting variation of the operation voltage of thememory device.
 4. The circuit claim 2, wherein the first delay circuitfurther comprises a fourth delay circuit for delaying a signaltransferred from the third delay circuit for a predetermined time. 5.The circuit of claim 4, wherein a delay time of the fourth delay circuitis controlled by an address signal and the fourth delay circuit is adelay path used in a test mode of the memory device.
 6. The circuit ofclaim 2 wherein as the frequency of the clock signal increases, a pulsewidth of the first signal is narrower.
 7. The circuit of claim 2,wherein as the operation voltage of the memory device increases, a pulsewidth of the first signal is wider.
 8. The circuit of claim 1 whereinthe at least one of a NAND gate and a NOR gate is a NAND gate.
 9. Amethod of controlling an enabling period of an internal control signalaccording to varying operating frequency in a memory device, with thecircuit of claim 1, the method comprising: providing the circuit ofclaim 1 ; changing a pulse width of an input signal in the pulse widthadjusting circuit; buffering the signal outputted from the pulse widthadjusting circuit in the signal transmission circuit; and outputting afirst signal in the output circuit to control the operation of the databus of the memory device in response to the signal outputted from thesignal transmission circuit, wherein as the clock signal durationshortens, the pulse width of the first signal is narrower.
 10. Themethod of claim 9 further comprising: receiving the input signal by asecond delay circuit in the first delay circuit; and receiving a signaltransferred from the second delay circuit by a third delay circuit,wherein a delay time of the second delay circuit varies in accordancewith variation of the frequency of the clock signal, wherein a delaytime of the third delay circuit varies in accordance with variation ofan operation voltage of the memory device, and wherein an output signalof the third delay circuit is applied to the at least one of a NAND gateand a NOR gate.
 11. The method of claim 10, further comprising:detecting variation of the frequency of the clock signal in a frequencydetector of the first delay circuit; and detecting variation of theoperation voltage of the memory device in a voltage detector.
 12. Themethod of claim 10, further comprising: delaying a signal transferredfrom the third delay circuit for a predetermined time by a fourth delaycircuit in the first delay circuit.
 13. The method of claim 12, whereina delay time of the fourth delay circuit is controlled by an addresssignal and the fourth delay circuit is a delay path used in a test modeof the memory device.
 14. The method of claim 10, wherein as thefrequency of the clock signal increases, a pulse width of the firstsignal is narrower.
 15. The method of claim 10, wherein as the operationvoltage of the memory device increases, a pulse width of the firstsignal is wider.